We demonstrate a wideband and high power distributed amplifier (DA) using an 0.5 μm indium phosphide (InP) double heterojunction bipolar transistor (HBT) process. For the first time, a triple stack HBT topology is used in an InP DA to achieve high power and high linearity. The 1.2 mm x 0.75 mm fabricated chip exhibits a measured gain of 16 dB, maximum output power of 19.5 dBm and output third order intercept point (OIP3) of 27.5 dBm. The bandwidth covers 1.5 – 88 GHz. This makes the gain-bandwidth product (GBP) 546 GHz. To the best of the authors’ knowledge, this work reports the highest output power and OIP3 over a wide bandwidth among all published distributed amplifiers to date.

A 410 GHz fully-integrated power amplifier (PA) is demonstrated using a 0.15-μm GaAs pHEMT process. This PA employs a compact structure with 4-parallel 3-stacked-FET cells to obtain a broadband power performance within a very small chip size. The measurement results of this PA in the frequency range of 410 GHz show a gain flatness of 13.5±1.5 dB, a maximum input return loss (S11) of -9 dB, a maximum output return loss (S22) of -7 dB, and a 3537 dBm output power with the corresponding power added efficiency (PAE) of 2532%. To the author’s knowledge, this is the first GaAs PA ever reported which covers the frequency range of 410 GHz and achieves the combination of output power and instantaneous broadband performance within a chip size of 1.6mm×1.6 mm.

This work presents the design and implementation of a flat-gain, efficient and wideband stacked distributed power amplifier (SDPA) in 0.13 µm CMOS technology. To get high output swing along with a reasonable gain, a four-transistor stack is utilized in four sections. Voltage alignment at the drain of each device in the stack is obtained by allowing a small AC swing at the gate by voltage division between Cgs and the external gate capacitor. Interstage matching is performed through peaking inductors. Further, the uniform distributed amplifier topology is adopted to control the impedance at each current injecting node from the stack to the artificial drain lines resulting into flat gain. Measured results show at least 10 ± 0.3dB small-signal gain from 2-16 GHz. The SDPA demonstrated a saturated output power of 18 dBm with peak efficiency of 17% and an OIP3 of 22 dBm occupying an area of 0.83 mm2.

A fully integrated K-band transformer based power amplifier with neutralization technique is proposed and fabricated in 90-nm CMOS technology. Several cascode cells are combined together as differential power cells. On-chip transformers and current combing topology are used to combine amplifiers as well as to reduce the problem of output power loss. In order to improve the overall stability, neutralization structure is utilized in the combined cascode cell. The measurement result demonstrates 14.1-dB small-signal gain, saturated power (Psat) of 24.4 dBm, and output 1-dB compression point (OP1dB) of 21.7 dBm at 24 GHz. The peak power added efficiency (PAE) achieved by this PA at 24 GHz is 28%. The chip size is 0.526 mm2 with all pads. To the authors’ knowledge, this circuit presents a superior power and efficiency performance compared with the reported K-band CMOS PAs.

First-ever realization of a W-band power amplifier (PA) millimeter-wave monolithic integrated circuit (MMIC) utilizing GaN-based Tri-gate high-electron-mobility transistors (HEMTs) is presented in this paper. Superior device- and circuit-level performances over conventional GaN HEMTs are proven to be empowered through implementation of the novel Tri-gate topology which exhibits a 3-dimensional gate profile. The measurements of the fabricated MMIC yield up to 30.6 dBm (1.15 W) of output power in the frequency range 86–94 GHz with 8% power-added-efficiency (PAE) and more than 12 dB transducer power gain. The achieved results demonstrate the promising potential of Tri-gate GaN technology towards high-performance millimeter-wave PA designs.

This paper presents a 0.49 terahertz (THz) radiating source in 40 nm CMOS. The radiating source is composed of a cross-coupled oscillator, a differential tripler, a substrate integrated waveguide (SIW) based harmonic power extractor (HPE) and a folded dipole antenna. The HPE can optimize third harmonic power extraction and provide suppression of unwanted lower order harmonic leakage. The measured equivalent isotropically radiated power (EIRP) of the radiating source is -4.1 dBm. According to simulated antenna gain of 11.2 dB, the output power and DC-to-THz efficiency of the signal source can be calculated as -15.3 dBm and 0.173%, respectively. The output frequency can be tuned from 475 to 511 GHz within 10 dB EIRP variation.

A wideband THz imaging transmitter in a 65-nm bulk CMOS process is demonstrated. The TX generates 0.73 mW of peak output power at 448 GHz and operates over a setup-limited bandwidth of 15% by using an energy efficient frequency quadrupler implemented with a cascade of two frequency doublers, and by co-optimizing the power driver and accumulation-mode symmetric MOS varactor frequency tripler. The TX has the highest reported single-element power density and 0.8% (1.66% w/o PLL) DC to RF conversion efficiency after including simulated PLL power consumption is the highest reported among CMOS and SiGe HBT sources operating above 0.3 THz.

This paper demonstrates a fully-integrated Cartesian feedback loop transmitter (TX) in CMOS 65nm. LO path phase shifters, aiming at compensating the phase misalignments between up- and down-conversion mixers or RF path phase delays, are improved by an interpolation scheme to ensure consecutive 360° tuning range. Power supplies of different circuit blocks are separated to cut off the nested feedback loops formed between the power buses and the circuit blocks for the stability consideration. The transmitter delivers 18.5dBm output P1dB at 9GHz. Over 10dB suppression ratio of intermodulation products in the two-tone test is achieved, and ACPR is improved by 9dB using a 2Mbps 16QAM testing signal. The maximum IM3 suppression is over 15 dB at medium output power levels.

A 8 Gbit/s current-mode automatic gain control (CMAGC) am-plifier with a reconfigurability between an internal closed loop control (analog AGC) and external baseband feedback control (digital AGC) is introduced in this paper. By using the p-n diode in CMOS technology, this CMAGC achieves an exponential vari-able gain control and a logarithmic power detection with more than 24 dB dynamic range. The proposed CMAGC consumes a maximum 48 mW dc power from a 1.2 V supply voltage and the core design occupies only 0.029 mm2 die area.

Interferences injected to an RF circuit may strongly deteriorate the electrical performance. Parasitic coupling via substrate is one of the dominant interference transmission mechanisms in highly integrated systems. The effect of substrate coupling becomes more critical at higher circuit frequencies. This poses a particular challenge for millimeter-wave systems, since isolation become less efficient with an increasing frequency. This paper presents an experimental study on coupling via bulk silicon and RFSOI substrates. We investigate in measurement up to 110 GHz efficiency of several isolation techniques, such as triple-well, p+ and n+ guard-rings and use of undoped highly resistive region. Additionally, RF-SOI substrates are known to be beneficial for higher crosstalk isolation. However, also this isolation degrades at higher frequencies. Hence, we investigate in measurement up to 110 GHz the isolation via low-resistivity and high-resistivity trap-rich SOI substrate variants. Test structures were realized in 40 nm bulk CMOS and 45 nm RF-SOI.

This paper presents the design, the realization and the power characteristics of plastic low cost packaged symmetric Doherty Power Amplifiers (DPA) operating in the 5.5-6.5GHz bandwidth. A single input (SI-DPA) and a dual input (DI-DPA) DPA are proposed based on two power bars composed of two GaN HEMT cells. Input and output matching networks are designed on passive GaAs MMIC technology. The measured power results under continuous wave signal at the same input level of a conventional Deep class AB PA in the one hand, the SI-DPA and the DI-DPA in the other hand are presented. To our knowledge, it is the first published SI and DI-DPAs working at C band, designed using Quasi-MMIC technology and assembled in plastic package.

A novel semi-integrated three-way 1:2:1 Doherty amplifier architecture is proposed to address the high efficiency / low cost / small footprint challenges of small cells. Using this approach, a 35 x 35 mm2 amplifier based on a 60 W MMIC is designed for the 2.11 to 2.17 GHz frequency band. It achieves a maximum gain of 27.4 dB, an average efficiency of 48.5 % at 8 dB back-off, and can be linearized to lower than -58 dBc ACPR level with a 20 MHz wide LTE signal.

A highly linear fully integrated 40 W 2-stage Doherty power amplifier (DPA) for 4/5G communication systems is introduced. By using the digital pre-distortion (DPD) technique, the proposed DPA achieved -58 dBc ACLR with 42% total line-up efficiency at 39 dBm average output power with a 365 MHz IBW at a center frequency of 2 GHz. To extend instantaneous bandwidth (IBW), the proposed power amplifier (PA) is employed with linearity enhancement circuitry to minimize low frequency second-order term. To the best of the authors’ knowledge, this is the first 2-stage RFIC DPA which can be linearized to this level with 365 MHz signal bandwidth and achieve this level of efficiency.

The design and performance of a MMIC power amplifier chip set covering the 2 to 18 GHz band using 0.2μm GaN HEMT technology is presented. Measured results of the Output MMIC show an average output power of 20.7 W and an average PAE greater than 27% across the 2 to 18 GHz band, while the Driver MMIC demonstrates an 8 to 10 W capability with an average PAE of 28% across the 2 to 18 GHz band. These results are among the highest power and PAE reported from MMICs covering this bandwidth.

We demonstrate the first silicon photonics enabled hyper-wideband wireless link with an instantaneous bandwidth of 12 GHz, which is 85% of the center frequency of 14 GHz. The silicon photonics based RF receiver consists of a four-channel optical phase encoder, an integrated hybrid-silicon mode-locked laser, and two silicon ring notch filters. The received CDMA RF wireless signal is correlated to baseband using coherent optical heterodyne at a data rate of 3 Gbps error-free with electronics bandwidth of only 3 GHz. Hyper-wideband RF transmission allows for data obfuscation and increased jamming resistance from narrowband interferers. The narrowband silicon photonic ring filters allow for further interference rejection of greater than 27 dB tunable over the full 20 GHz of RF spectrum.

We present a novel photoconductive terahertz emitter, which offers significantly high terahertz radiation power levels through three-dimensional light confinement near terahertz radiating elements. Arrays of plasmonic nano-antennas fabricated on a photo-absorbing semiconductor substrate are used as the terahertz radiating elements. The plasmonic nano-antenna arrays are designed to offer high radiation resistance over a broad terahertz frequency range. An optical reflector layer is embedded inside the substrate to spatially confine and absorb a major portion of an incident optical pump beam near the plasmonic nano-antennas. Therefore, very efficient ultrafast photocurrent can be generated and coupled to the plasmonic nano-antennas for high-efficiency terahertz radiation generation. We experimentally demonstrate record-high terahertz radiation powers as high as 11.4 mW over 0.1-5 THz frequency range with 2.3% optical-to-terahertz conversion efficiency.

In this paper, a linear driver for optical modulators in a 0.13 μm SiGe:C BiCMOS technology with fT/fmax of 300/500 GHz is presented. The driver is implemented following a distributed amplifier topology in a differential manner. In a 50‑Ω environment, the circuit delivers a maximum differential output amplitude of 4 Vpp, featuring a small-signal gain of 13 dB and 3‑dB bandwidth of 90 GHz. Time-domain measurements using OOK (up to 56 Gb/s) and PAM‑4 (at 30 Gbaud) are performed, demonstrating the maximum output swing and linearity of the driver. The output power to power dissipation ratio is 3.6%. To the best knowledge of the authors, this is the first time a linear driver for optical modulators demonstrates such bandwidth.

An optical ring resonator (ORR) based integrated optical beamforming network (OBFN) for a W-band millimeter wave phased array antenna is reported. The delay response of a 3-ORR delay line is optimized and dynamic tuning ranges of 208.7 ps and 172.4 ps for the true time delay bandwidths of 6.3 GHz and 8.7 GHz are achieved. Moreover, all of the delay paths are successfully tuned with 4.2 ps delay difference from the neighboring paths. Eye diagrams of a 3 Gbps NRZ OOK modulated signal are measured to show that no noticeable signal deterioration is induced by the OBFN chip.

Based on two low-noise amplifier (LNA) millimeter-wave integrated circuits (MMICs), this paper reports on a comparison between a 35-nm and a 50-nm gate-length metamorphic high-electron-mobility transistor technology. The LNA targets applications in an extended W-band with an operating frequency between 67-116 GHz. Both MMICs yield a scalar linear gain of at least 20 dB for more than an octave bandwidth. The average scalar linear gain of the 35-nm (LNA 1) and 50-nm LNA (LNA 2) is 26.2 dB and 25 dB, respectively. The measured noise figure of LNA 1 and LNA 2 achieves an excellent average value for the entire W-band (75-110 GHz) of 1.9 dB and 2.1 dB, respectively. To the best of the authors’ knowledge LNA 1 is the first MMIC which yields an average noise figure of 1.9 dB over the entire W-band.

We present the development of a wideband low-noise amplifier MMIC in the D-band with a smart combination of coplanar transmission lines and active devices to minimize noise figure. The identical three-stage LNA has been realized in metamorphic HEMT technologies with 100 nm and 50 nm gate length. The 50 nm LNA MMIC achieves a linear gain of 30.8 dB together with a bandwidth of 67 GHz up to 164 GHz and a noise figure of 3.0 dB. The performance of 100 nm LNA is slightly worse.

A WR-3 (220 – 330 GHz) low-noise amplifier (LNA) circuit was realized by using a 35 nm InAlAs/InGaAs based metamorphic high electron mobility transistor (mHEMT) technology in combination with grounded coplanar waveguide topology (GCPW) and cascode transistors, thus leading to a very low noise figure in combination with high gain and large operational bandwidth. The packaged LNA achieved a maximum gain of 29 dB at 314 GHz and more than 26 dB in the frequency range from 252 to 330 GHz. An average room temperature noise figure of 6.5 dB was measured between 280 and 330 GHz. Furthermore, the LNA circuit has been used to realize a very compact WR-3 single-chip receiver module, demonstrating a conversion gain of 7.5 dB and a noise figure of 11dB at the frequency of operation.

A ultra-wideband (UWB) low noise amplifier (LNA) was designed and fabricated in 0.18um CMOS technology. The successful integration of current-reused and forward body biasing (FBB) techniques in a cascade amplifier can enable an aggressive scaling of the supply voltages, VDD and VG1 to 1.0V and 0.53V. The low voltage feature from FBB leads to more than 50% saving of power dissipation to 5.2mW. The measured power gain (S21) can reach 10.55~12.6dB and noise figure (NF50) is 3.2~3.95 dB through the UWB (3~10.5GHz). This UWB LNA with small chip area (0.69mm^2) provides a solution of low voltages, low power, and low cost.

This paper presents a W-band phased-array receive front-end in 32-nm CMOS silicon-on-insulator (SOI) technology. The measured performance shows an average gain of 17-18 dB and a NF of 5 dB at 94-96 GHz. The phase shifter is based on passive switched networks with a measured RMS phase and gain error of < 6 and < 1 dB at 94-96 GHz, respectively. The front-end consumes 24.3 mW from 1.3 V. According to the author’s knowledge, the NF and power consumption is state-of-the-art for silicon-based phased-array receivers at W-band frequencies.

This paper presents the design and characterization of a Doherty power amplifier for small cells applications in the 1.7–2.7GHz band. A quasi-monolithic realization is selected for its cost advantages when compared to a fully-monolithic solution, and relies on GaN HEMT active devices and passive networks on GaAs substrate. A lumped elements Doherty combiner is designed to maximize the bandwidth at which the power amplifier shows high back-off efficiency, that results higher than 37% in the 1.7–2.7GHz band in measurements. The dual-input topology permits high flexibility in the optimization of performance, in particular in terms of bandwidth. The fabricated Doherty favourably compares to similar previously published power amplifiers.

This paper presents a GaN-HEMT DPA IC based on a compact load network for LTE small-cells. The gate widths of the transistors for the carrier and peaking amplifiers are optimized to have the same load impedance of 100 Ω. A shunt inductor is added to compensate for the output capacitor of each transistor with parallel resonance. A π-type high-pass impedance transformer based on lumped components is used for the load impedance modulation. Parallel inductors from the resonant circuit and the impedance transformer are merged for further simplification. As a result, only two inductors remain in the load network. For verification, a 2.6 GHz DPA IC with an on-chip load network and input matching networks was designed and fabricated using a 0.4 µm GaN-HEMT process.

In this paper, novel broadband Doherty power amplifier design for multi band handset applications, which requires only two components for output network, is proposed. Based on simplified output network, the proposed Doherty power amplifier is analyzed. The proposed Doherty power amplifier is demonstrated experimentally with InGaP-HBT. A PAE of 45.0% and an E-UTRA ACLR of -36.4 dBc at an average output power of 26.4 dBm are measured at 800 MHz under LTE 10 MHz, QPSK, 12 RB operation, and the efficiency improvement from Class AB operation achieves 12%. Moreover, the proposed Doherty power amplifier maintains more than 41.0% efficiency with an E-UTRA ACLR of below -35.7 dBc from 700MHz to 925MHz, corresponding to 28% fractional bandwidth.

We propose a new modulating load range for a Doherty power amplifier (DPA) that will maintain maximum drain voltage swing and consequently peak efficiency in over 6-dB power back-off (PBO). At 6-dB PBO, the real part of the new modulating load seen by the main amplifier is less than 2*Ropt. The new load range allows for the design of a compact, low loss output matching and combiner circuit and a simple single drain bias line for the main and auxiliary amplifiers. The proposed 2-stage DPA using the new modulating loads is designed at 15 GHZ in a 0.15 µm enhancement mode (E-mode) Gallium Arsenide (GaAs) pseudomorphic high electron mobility transistor (pHEMT) process. The proposed DPA achieves a measured Psat of 27 dBm, a peak power added efficiency (PAE) of 41% and a PAE of 34% at 6 dB PBO with a gain of 17 dB.

The post-matching (PM) topology is an effective approach to broaden the bandwidth of Doherty power amplifiers (DPA). However, its efficiency has been limited because previous works only considered the fundamental frequency termination, and not the harmonics. In this paper, a modified phase compensation network is used in the PM Doherty topology to realize a third harmonic open as viewed by both carrier and peaking device in the Doherty region. Hence, the efficiency enhancement in the en-tire Doherty region can be achieved. For demonstration purpose, a high efficiency Doherty prototype is devised based on two iden-tical 10W GaN HEMTs. Measurement results show that at least 50% drain efficiency is achieved at 6 dB back-off power from 1.3 to 1.8 GHz.

The paper extends the concept of waveform shaping for back–off applications which can be applied to realize power amplification sub-blocks in load modulation based power amplifiers. The proposed theory starts with deriving the intrinsic current and voltage waveforms as a function of output power back-off factor. Thereafter, a design methodology is proposed to optimize the performance of power amplifier for back–off requirements within a limit of 3 dB gain compression. For experimental validation, the implementation is carried out using a 1.95 mm gallium nitride (GaN) die. The single-ended PA is designed to operate as a carrier PA in a 35 dBm average asymmetric Doherty configuration (44 dBm peak power). The PA exhibits a drain efficiency of 78% at an average output power of 35 dBm at a frequency of 2.6 GHz.

The 300-GHz band enables ultrahigh-speed wireless communication because of its vast frequency range. We present a wireless link with a 300-GHz-band CMOS transmitter that im-proves the system signal-to-noise ratio (SNR) by using a frequen-cy-doubler-based subharmonic mixer called a “square mixer” and an architecture with image and local oscillator (LO) sup-pression. It achieved wireless digital transmission at 56 Gbit/s over 5 cm with 16-QAM. In addition, we compare the perfor-mance of wireless links using a figure-of-merit (FoM). This wire-less link has an approximately 7.5 times higher FoM than a re-cently reported wireless link based on a CMOS transmitter.

The low loss and wide dispersion-free bandwidth of Sommerfeld-wave propagation on a single conductor wire (SCW) promises energy-efficient high data rate links. The first fully-integrated end-to-end wireline transceiver system on a SCW using Sommerfeld-wave propagation mode is demonstrated using a 60-GHz carrier frequency. Implemented in 65-nm CMOS, the proposed system includes on-chip radial-mode antennas as well as integrated serializers, 60-GHz OOK modulator, demodulator, deserializers and clocking. The link achieves 7 Gb/s data rate across 20-cm of 26AWG bare copper wire (diameter = 0.4 mm), while consuming 70.9 mW of power. Operating at 6 Gb/s and 7 Gb/s, this work achieves BER 1e-12 and 1e-5 respectively.

Energy-efficient, multi-Gb/s wireless links are of interest for short-range board-to-board links within server chassis/enclosed server platforms. In this paper, we propose to leverage the small physical size/large available bandwidth of mm-wave systems to demonstrate combined frequency and spatial modulation in a mm-wave TX, targeting links operating in slow-varying channels. A pulsed mm-wave digitally-controlled oscillator (DCO) provides low-power FSK capability, while variable pulse trigger delay achieves controlled relative phase between TX elements for low-power space-shift keying (SSK). A two-element 65-nm CMOS TX prototype is packaged with PCB antennas to demonstrate a 2-FSK/4-SSK 3-Gb/s TX up to 60-cm with 21.4 mW power consumption, achieving ~7.1 pJ/bit.

This paper presents a high energy-efficiency high bandwidth-density dielectric waveguide based sub-THz interconnect, including a near-field coupled low-loss, wide-bandwidth sub-THz channel and a high energy-efficiency transceiver. The channel loss is 4.0 dB with 59 GHz 3-dB bandwidth. The transmitter output power is -1.7 dBm with 6.7 mW of DC power consumption, and the receiver DC power consumption is 7.5 mW. The energy efficiency is 2.8 pJ/b, and the bandwidth density is 33.3 Gbps/mm2.

Recent advances in both high power millimeter wave (mmW) Gallium Nitride (GaN) technology and high-speed System on Chip (SoC) modem technology has enabled the development, fabrication, and field testing of a high speed, long range wireless datalink with fiber equivalent speed. The link exhibited nearly an 80 Gbps bi-directional data rate (40 Gbps in each direction) over a range of 16km. This was accomplished by using a combination of frequency and polarization multiplexing to combine a total of eight ~10 Gbps modem channels on the lower (71-76 GHz) and upper (81-86 GHz) E-band channels. Each modem channel was separately up-converted and amplified with a Gallium Nitride (GaN) power amplifier. Frequency multiplexing was accomplished at E-band (post-amplification) to maintain high Power Added Efficiency (PAE) in the power amplifiers.

This paper presents a wideband supply-modulated (SM) system with a floating ground RF power amplifier and a reverse buck topology DC/DC converter. The power amplifier and the reverse buck converter are based on microwave GaN technology. The system is operating at 1620 MHz and 40 V supply and shows 39% overall efficiency at an average output power of 14.6 W for an 8 MHz OFDM modulated signal with 8.6 dB PAPR. The implemented floating-ground RF power amplifier accommodates signals with up to 40 MHz bandwidth. The reverse buck converter switches at 45 MHz with a PAE of 80 – 91% over duty cycles from 40 – 100% equivalent to supply voltages of 16 – 40 V. For the first time a reverse buck topology system enabling GaN switching operation referred to ground is shown in dynamic operation with performance similar to or exceeding classical systems.

Model-based nonlinear embedding is applied for the first time to the design of an asymmetrically-driven class-F Chireix power amplifier. The embedding model is used to determine the optimum load impedances for the fundamental and multi-harmonics required at the package planes such that the two intrinsic transistors operate with a recently reported ideal current-based Chireix combiner. This PA designed using embedding is found to require asymmetrical amplitude and phase modulated input drives to support the targeted equal power input signals at the intrinsic reference planes. The Chireix PA designed exhibits a peak drain efficiency of 79.6 % and power added-efficiency (PAE) over 77/71% around peak power (43/44 dBm) and 55% at 8dB backoff power (36dBm) at 2 GHz measured with a large-signal network analyzer (LSNA). Using a lookup table driver, the PA average drain efficiency is 50% for a 5 MHz W-CDMA signal with 9.3 dB PAPR and -41.5 dBc ACPR.

This paper present a multi-band Doherty power amplifier (DPA) implemented in a 0.18um CMOS SOI. In order to enable the multi-band operation, the proposed DPA employs tunable matching networks with digital controls that are set via serial RFFE commands. Using digital pre-distortion (DPD) techniques, the proposed Doherty PA improves efficiency over a wide output power range and over multiple bands of operation between 1.55GHz to 2.3GHz. By utilizing linearizer circuits, tunable matching networks and DPD, the measured PAE with the R99 modulated signal can be as high as 50.1% at 27.8dBm output power while meeting ACP specifications.

The Load Modulated Balanced Amplifier (LMBA) uses a control signal (CSP), injected to the normally terminated port at the out-put coupler of a balanced amplifier (BA), to modulate the BA transistor’s impedance. The hybrid circuit demonstrator de-scribed here uses metal-backed multilayer organic substrate and GaN discrete devices. Maximum output power levels above 39.5 dBm are achieved at around P3dB. DE above 60% is seen be-tween 4.5 and 7.5 GHz for power back-off to 7 dB with a fixed CSP of 1 W, and the bias 18 to 28 V Index Terms—power amplifier (PA), Doherty, load modulation, GaN, balanced amplifier, broadband, octave.

This paper presents a hybrid supply modulator including Buck-Boost converter, which has wide battery operating range for cellular envelope tracking applications. The output voltage swing is boosted up to 4.5V by an integrated BB converter as supply of linear amplifier. A selective supply voltage of the switching amplifier and a reverse current sensing circuit are employed to prevent the reverse current. The proposed automatic current ratio controller between the linear amplifier and the switching amplifier provides robust performance against the battery voltage variation. The proposed SM supports LTE20MHz envelope signal with 76% efficiency at 800mW output. Adapting the SM to a PA at FDD Band3 with LTE 10MHz, the implemented ET-PA achieves 41.6% of power added efficiency (PAE) at 27dBm PA output power, while achieving -40dBc of E-UTRA ACLR and -137dBm/Hz of RX band noise. The chip is implemented in 0.13μm CMOS process, and the die size is 5.0mm2.

This paper presents an active up-converter realized as hetero-integrated module in InP-on-BiCMOS technology. It consists of a fundamental Voltage Controlled Oscillator (VCO) in 0.25 μm BiCMOS technology and a frequency multiplier followed by double balanced Gilbert mixer cell in 0.8 μm transferred substrate (TS) InP-HBT technology, which is integrated on top of the BiCMOS MMIC. The fundamental VCO operates at 54 GHz. The module achieves a single-sideband (SSB) power up-conversion gain of 2.5 dB and -3.5 dB at 82 GHz and 106 GHz, respectively. It exhibits > 25 GHz IF bandwidth. To the knowledge of the authors, this is the first heterointegrated mm-wave module reported so far.

A very wideband GaAs MMIC Schottky diode frequency doubler has been designed and tested; it has at least a 10-66 GHz output frequency range with measured conversion loss of 9 to 15 dB. It has -15 to -25 dBc fundamental suppression, -22 to -35 dBc 3rd harmonic suppression, and 15 to 20 dB input return loss. It is singly balanced with a broadside coupled 4:1 transmission line transformer that provides wideband impedance match and input ground return. This appears to be the widest operating bandwidth reported for a GaAs MMIC diode frequency doubler. A family of frequency doublers and mixers has been designed and built that use this new circuit topology.

A compact wide-band mm-wave frequency divider is presented. By utilizing a multi-injection scheme in a fully differential ring oscillator, a wide locking range is achieved. The multi-injection scheme is implemented such that no phase shifter is required for the optimum operation. The chip is fabricated in a 130nm BiCMOS process. The structure is compact with a core area of 0.0016 mm^2. With an input power level of 0dBm a locking range of 12-61GHz (134%) with a division ratio of 2 is achieved. The divider consuming 10.4mW of DC power. To the best of our knowledge, this is the widest locking range among all the mm-wave frequency dividers.

In this paper an active phase shifter with high linear frequency dependency is presented for a FSK quadrature demodulator. The circuit is based on a coupled resonator to increase the linear phase shifting range and bandwidth. A capacitor bank, implemented as a digitally controlled artificial dielectric transmission line, is used to realize the phase shifting operation. The design methodology is explained and measurements of an implementation in a 28nm bulk CMOS are given. The design has a phase range of 123 degrees and a phase resolution of 7.2 degrees with a frequency dependent phase difference of 12.2 degrees/GHz. The circuit occupies an active area of 0.01mm² and draws a current of 9.5 mA from a 900mV power supply.

This paper presents a performance evaluation of an original highly efficient and linear GaN-HEMT Vector Power Modulator (VPM) based on the design of a two-stage saturated variable gain (SVG) amplifier and a multi-level discrete supply modulator. The proposed novel architecture for transforming a digital baseband data stream into an RF Vector modulated power waveform (RF Power DAC) is validated using a specific laboratory test bench. The main objective of this study is to merge signal modulation and DC to RF energy conversion functions into a single and compact GaN based mixer-less circuit. Using high-voltage 50V GaN technology, a 20WS-band vector power modulator having overall average PAE of around 40% is reported. The concept demonstrator is experimentally validated up to 100Msymbols/sec 16-QAM modulation scheme. Functional time alignment with phase and amplitude compensation procedure focusing on measured constellation at 40 Msymbols/sec enables to reach excellent EVM performances of around 3.2%.

Two 250-nm InP HBT power amplifiers operating between 180-265 GHz are reported. A 3-stage, 8-PA cell design demonstrates S21 exceeding 25-dB between 202-257 GHz and 20-dB between 194-265 GHz. Peak output power is 140-mW at 200-GHz with 5.1% PAE. The PA Psat RF power is at least 100-mW from 190-235 GHz, 82-mW from 183-245 GHz, and 50-mW from 183-263 GHz. A 3-stage, 16-PA cell design demonstrates S21 gain exceeding 24-dB between 200-255 GHz and 20-dB between 194-262 GHz. Peak output power is 248-mW at 200-GHz with 4.1% PAE. The PA RF power is at least 200-mW from 195-215 GHz, 170-mW from 190-220 GHz, and 100-mW from 185-255 GHz. Improvements to state-of-the-art include: 13% increase to the maximum PA power above 200-GHz, first reported 200-mW PA with 20-GHz (195-215 GHz) operation, highest power reported above 240-GHz, first demonstrated 100-mW power to 255-GHz, and 70-GHz (16-cell) and 80-GHz (8-cell) PA large-signal bandwidth.

In this letter, the first 670 GHz multiplier chain with integrated buffer amplifiers is reported. The x36 multiplier chain uses a 25 nm InP HEMT MMIC technology with > 1.5 THz fMAX. The chain consists of five packaged MMICs in three split-block waveguide housings with each multiplier incorporating an integrated output buffer. We report an output power of 1.8 mW at 680 GHz when measured at room temperature, with a total DC power consumption of only 1.7 W. This is believed to be the highest DC efficiency reported for a complete multiplier chain at this frequency range.

This paper presents a 70–110 GHz single-chip SiGe reflectometer for one-port vector network analyzer (VNA). Two directional couplers are implemented together with two high-linearity heterodyne receivers on a single chip at 70-110 GHz. In addition, a x4 frequency multiplier chain is also implemented on the same chip. A CPW coupled-line directional is used with a shielded gound plane for improved isolation and directivity. The dynamic range of the receiver is 110–115 dB at 70–110 GHz with 10 dB back-off and 10 Hz resolution bandwidth. The SiGe chip is 5.86 mm2 and consumes 440 mW from a 2 V supply. The chip is mounted on a printed circuit board, and RF and LO signals are applied using probes. A 95 GHz bandpass filter is measured as the device-under-test and the results obtained using the on-chip VNA and a commericial VNA show good agreement over a wide freq range.

This paper presents a J-Band (220-325 GHz) subharmonic receiver front-end implemented in 130 nm SiGe BiCMOS . The receiver chip includes integrated LO amplifiers and wideband Marchand baluns at the RF and LO ports. The subharmonic down-conversion mixer is based on a novel topology having a Gilbert cell with stacked switching quads, which are fed by equal-phase local oscillator signals. A very wideband operation is achieved by directly matching the RF input signal to the emitter terminals of the switching quad and not using a transconductance stage. On-wafer measurements of the receiver show a peak conversion gain of 11 dB, a minimum double side band noise figure of around 16 dB and a simulated input compression point of -7 dBm, while consuming a total DC power of 160 mW. The chip demonstrates the highest 3-dB conversion gain bandwidth and compression point for Si-based receivers operating above 200 GHz.

This paper presents a W-band phased array receive (Rx) channel that employs a quadrature-hybrid based power-domain phase interpolator for a power-efficient multi-bit phase synthesis. The Rx channel implemented in 0.13 μm SiGe BiCMOS achieves 137 dB∙Hz dynamic range (DR) with total 18 mW DC power consumption at 94 GHz. This leads to 7.6 dB∙Hz/mW of Rx DR efficiency figure of merit, one of the best power efficiencies reported so far in integrated phased array receivers at mm-Wave frequencies. The measured average gain is 21 dB at 94 GHz and RMS gain variation over 4-bit phase states is < 1.4 dB (3-dB BW: 92-100 GHz). The measured RMS phase error is < 2.5º at 94 GHz. The measured NF is 5.7-6.7 dB for all over the phase states and typical IP-1dB is -31.4 dBm at 94 GHz. The core chip size of the receiver is 1.2×0.58 mm^2.

This paper describes the first-reported development of a micromachined differential probe for direct on-wafer measurements operating in the WM-1295 (140—220 GHz) frequency band. Design and fabrication of the probe, which includes integrated circuitry for converting the input of a single-ended vector network analyzer to differential mode, are described and an on-wafer calibration procedure for extracting the probe mixed-mode scattering parameters.is detailed

We present a novel waveguide-to-suspended stripline loop-probe transition operating over the entire WR-1.0 waveguide band. The loop probe is designed for broadband response with simu-lated RL > 15 dB, and has an integrated DC return path, which can also be extended for biasing. The measured insertion loss for a back-to-back configuration is 1 – 2 dB in almost the entire frequency range of 750 – 1100 GHz.

In this work, a 500-750 GHz (WM-380) RF micro- electromechanical (MEMS) DC contact switch is realized and reported. This switch is integrated with a coplanar waveguide (CPW), which is designed with a characteristic impedance of 50 Ω. The structure is fabricated on high resistivity silicon with top isolation silicon dioxide layer of 100 nm. Under a threshold voltage of 60 V, electrostatic force actuates the switch into “ON” state. Switch design and its calibration are discussed. Measurements show the insertion loss to be 0.7-2.7 dB in “ON” state with return loss greater than 12 dB. In the “OFF” state, isolation is better than 18 dB across the band.

A monolithic 3-bit phase shifter has been fabricated and demonstrates broadband and low loss performance from 220GHz to 240GHz. The phase shifter utilizes an ultra-low loss vanadium dioxide switch for phase state control. The design uses low-pass π-filter networks as phase shift elements for 45, 90 and 180 degree bits. This phase shifter’s mean insertion loss of 7.6 dB is 3dB lower than any other passive phase shifter we could identify in literature and comparable to the best active vector-sum devices. The RMS phase error is a competitive 6.8degrees at 230GHz and averages only 8dB over the band from 220 – 240GHz. This phase shifter’s complete circuit footprint is < 0.1mm2 easily fitting within (λ/2)2 ~ 0.4mm2 array spacing. We can find no passive phase shifter with comparable performance or compactness.

A low-cost and low-loss directional coupler implemented in the Silicon Image Guide (SIG) platform for high-end sub-millimeter-wave and THz integrated systems is proposed. A novel idea of supporting beams is used for facilitating the high precision fabrication of such a monolithic structure. A 3-dB coupler is designed and simulated for working at the centre frequency of 150 GHz. The simulated average phase unbalance of the coupler within the range of 145-155 GHz is less than 1 degree. The proposed coupler is fabricated using a fast and mask-free laser micro-machining process. The measured insertion loss and 1-dB bandwidth of the coupler are

This paper presents a wideband Doherty Power Amplifier (DPA) using 0.25um GaN on SiC High-Voltage technology suitable for Band-1 and Band-3 LTE Basestation applications This DPA puts out 85W Pavg and 500W peak power at the Doherty 50-ohm output, with relatively flat 45-49% average efficiency across 20% frequency bandwidth. To the knowledge of the authors, this is a first 2-Way DPA demonstration exhibiting such wideband high power levels while maintaining good efficiency and linearized performance, within 20% bandwidth. This work allows the use of one set of power amplifier discretes for multi-band operation (1.8-2.2GHz) of transmit systems, reducing cost and hardware complexity.

This paper presents a high-power Continuous-mode Doherty Power Amplifier (C-DPA) technique for base-station applications. By utilizing de-embedded model of active devices and allowing the two transistors modulating each other at harmonics frequencies, the proposed C-DPA exhibits improved power, efficiency and bandwidth. Based on the proposed technique, a demonstrating 200 Watt C-DPA is designed over 1.7-2.7 GHz. According to the measured results, over the 1GHz band, the designed DPA generates 52.7-54.3 dBm power at saturation and exhibits 40%-50.2% drain efficiency at -6dB power back-off. To the best of the authors’ knowledge, this is the state-of-the-art performance of high-power broadband DPAs for base-station applications. Furthermore, using a 10MHz, 7.5dB PAPR LTE signal, the fabricated DPA is measured and linearized over the full-band, verifying its ability of being linearized.

An integrated passive device (IPD) supporting both RF and baseband impedance matching is proposed that is directly suita-ble for high power, multiband amplifier applications. The im-pedance matching method and design techniques are discussed. As proof-of-concept, we present an LDMOS Doherty power amplifier (PA) with 400 W peak power using the proposed IPD to demonstrate 20% fractional RF bandwidth with low base-band impedance. Measurements of the Doherty PA with digital pre-distortion system indicate that the amplifier achieves over 40% drain efficiency at average Pout of 48.5 dBm with over 15 dB of gain during concurrent transmission of 3GPP Band 3 & Band 66 from 1.805 – 2.2 GHz while meeting ACPR of -53 dBc. The results represent over 2 times improvement of instantane-ous bandwidth capability over prior work and enables for the first time 395 MHz instantaneous bandwidth capability for high power downlink cellular infrastructure communication systems.

We propose an extended range Doherty power amplifier (DPA) to achieve high efficiency at 9-dB power back-off (PBO) using a novel loading impedance range. The proposed loading impedance range enables the auxiliary transistor to deliver more current so that symmetric devices can be used in the DPA and results in a compact and low loss output combining circuit. A 20-Watt DPA using Gallium nitride high electron mobility transistors (GaN HEMTs) at 3.5 GHz has been developed to demonstrate the concept. Measurements show power added efficiency (PAE) of 69% at 42.9 dBm saturation output power, PAE of 55% at 9-dB PBO, and gain of 12 dB. We believe our proposed DPA has the highest 9-dB PBO PAE of 55% among reported GaN DPA’s.

The design and performance of a high power Gallium Nitride (GaN) transmit-receive frontend MMIC is presented. The circuit is passive, does not require any external bias voltage and is mono-lithically compatible with GaN MMIC process technology. High power Tx port signals are directed to the ANT port and the Rx port is isolated and therefore protected from damage. Low power signals input to the ANT port are directed to the Rx port with minimal insertion loss. If the ANT port signal power exceeds some threshold, the circuit starts to limit the power to the Rx port protecting it from damage. Since the circuit does not require an external control voltage it will function normally providing fail-safe operation in the event of lost or disconnected bias. The MMIC results presented here demonstrate 0.7dB of transmit path loss, 1.0dB of receive path loss and 50W power handling over a 3.0-3.6GHz bandwidth.

High-performing GaN MMICs that can cover broadband appli-cations at W and D-Band have been fabricated and tested. A five stage 60-105 GHz LNA has >23 dB of gain across the band with 20dBm at 84GHz and a six stage D-Band LNA has 25 dB of gain with ~6dB projected NF from 110-170 GHz. A double balanced resistive FET mixer has -11 to -15 dB of conversion loss from 74–94 GHz. To our knowledge, these are the first reported GaN MMICs with high broadband gain at these frequencies.

This paper presents direct-coupled DC-50 GHz two-stage baseband amplifier topologies realized in a 35 nm gate-length InAlAs/InGaAs mHEMT technology. These are key components of future single-chip receiver MMICs for point-to-point communication systems. Three interstage coupling approaches are investigated: resistive coupling, a diode-level-shifter and a Kukielka amplifier. The Kukielka amplifier features the best performance in terms of gain-bandwidth-product and represents the state of the art for this topology. The investigated two-stage amplifier circuits achieve up to 21 dB gain and a 3 dB bandwidth of 53 GHz, requiring less than 300x300 µm² chip area. The presented level-shifter circuit has a 3 dB bandwidth of up to 150 GHz and an insertion loss of less than 3.5 dB.

An 80 nm InGaAs MOSFET W-band MMIC low noise amplifier (LNA) is presented. The technology uses 4" GaAs substrates with a molecular beam epitaxy (MBE) grown metamorphic buffer to realize the InGaAs/InAlAs device heterostructure. For a 2 x 20 µm gate width transistor a transit frequency fT of 226 GHz was extrapolated. A two-stage cascode configuration is used for the W-band LNA which was processed in MOSFET and HEMT technology for comparison. The MOSFET LNA achieves a linear gain of more than 17 dB in the frequency range from 75 to 105 GHz with an associated noise figure between 3.2 and 4.4 dB. To the best of the authors knowledge, this is the first reported InGaAs MOSFET millimeter-wave MMIC.

In this paper, we present a bang-bang phase detector (BBPD) and delay-line frequency discriminator (FD) based phase noise filter (PNF). With a larger phase detection gain, the BBPD based PNF enhances the phase noise cancellation and sensitivity by suppressing the charge pump (CP) noise. A time-amplifier (TA) and a 5 × voting machine are introduced together with the modified sense-amplifier-flip-flop (SAFF) to minimize the BBPD random noise. At 1 MHz offset, the maximum phase noise suppression is 23 dB and best phase noise sensitivity is -120.2 dBc/Hz and. Its phase noise suppression offset frequency is from 100 kHz to 8 MHz with 100 MHz input frequency range. The circuit is fabricated in a 65 nm CMOS technology and dissipates 98 mW power.

A current reuse triple-band signal generator is proposed which simultaneously generates a first, second, and third harmonic output signal from a 26.5-30.2 GHz fundamental voltage con-trolled oscillator (VCO). Transformer-based Gm boosting and passive 2nd harmonic extraction is proposed to achieve a good performance with exceptionally low power. A low-voltage modi-fied Gilbert cell mixer generates the third harmonic while re-quiring minimal voltage overhead, facilitating an efficient cur-rent reuse topology. The fabricated signal generation circuit consumes 8 mW of power and achieves a 13% tuning range and a measured phase noise of -121 dBc/Hz at 10 MHz offset. The pro-posed signal source demonstrates best-in-class performance among multi-band signal sources.

high performance X-band quadrature phase voltage-controlled oscillator (QVCO) for direct-conversion transceivers in 0.18-m CMOS is demonstrated. By using the novel 8-shaped transformer together with the current-reuse topology, the proposed design can be operated at reduced dc power consumption while maintaining low phase noise with suppressed Electro-Magnetic Compatibility (EMC) issues. Consuming a dc bias current of only 5.45 mA with the supply voltage of 1.8V, the QVCO has a frequency tuning range of 570 MHz, a phase noise of -121.12 dBc/Hz at 1MHz offset frequency away from the 10.48 GHz carrier frequency, and an FoM up to 191.9 dBc/Hz

This work presents the design of three low-phase-noise monolithic voltage controlled oscillators with a 2-µm InGaP-GaAs HBT technology for wideband satellite communications at C, X and Ku frequency bands. A large-signal design approach for the minimization of low-frequency noise up-conversion in conjunction with the optimization of the varactor-tuned integrated resonator were adopted for the minimization of phase noise generation. The C-band circuit implements a fundamental-frequency topology, whereas the X- and Ku- band oscillators are designed with a push-push configuration. The VCOs feature integrated output buffers for higher output power and improved load pulling. In the push-push VCOs, an integrated differential amplifier is used to provide an f0/2 prescaler output. Measured VCO frequency range of 3.31-4.17 GHz, 7.38-8.88 GHz, 10-12.28 GHz have been achieved, with maximum phase noise levels at 1 MHz offset from the carrier of -129 dBc/Hz, -124 dBc/Hz and -122 dBc/Hz respectively.

A V-band CMOS sub-harmonically injection-locked quadrature voltage-controlled oscillator (SILQVCO) is presented using 90-nm CMOS process in this paper. A transformer coupled topology is employed in the SILQVCO to enhance locking range and operation frequency. The measured free-running oscillation frequency is from 56.6 to 59 GHz with a tuning range of 2.4 GHz. With one-third sub-harmonic injection, the SILQVCO features an overall locking range of 3.5 GHz, a phase noise of -126.8 dBc/Hz at 1-MHz offset, and a RMS jitter of 54 fs integrated from 1 kHz to 40 MHz. The measured quadrature phase error and amplitude error are 0.32° and 0.26 dB, respectively. As compared with the prior art, this work has the best finger of merits in the millimeter-wave band.

A compact millimeter-wave oscillator in 90nm CMOS is presented. The proposed triple-push three-stage mutually coupled ring oscillator architecture significantly enhances the phase noise, out-put power, and power consumption. The measured phase noise is -114dBc/Hz at 10MHz offset with 28.6mW DC power consumption. The tuning range spans from 204.3GHz to 215GHz with the maximum output power of -7dBm at 210.8GHz. The FOM is -185.8dBc/Hz at 10MHz offset, and it remains below -179dBc/Hz within the entire tuning range.

In this paper, we propose a wide tuning range CMOS voltage control oscillator (VCO) at D band. In order to increase tuning range, we adopt switching transformer to change coupling coefficient. In addition, we cascade this 70 GHz VCO with frequency doubler to double frequency to 140 GHz. Combined-metal technique is used to improve Q of passive components and reduce insertion loss of transmission line for better phase noise. VCO tuning range is 14.5 % which is from 122.9 to 142.9 GHz. At 142 GHz, peak output power and peak efficiency is -2 dBm and 1.74 %, respectively. Phase noise is better than -96.5 dBc/Hz at all tuning frequency. The total DC power consumption is only 51 mW for 1 V supply voltage. To our best knowledge this VCO has wide tuning range and good DC to RF efficiency at D-band.

This paper presents a millimeter-wave (mm-wave) push-push voltage-controlled oscillator (VCO) in a 45 nm RF SOI CMOS technology. The circuit aims to meet specifications for FMCW radar applications requiring an ultra-wide PLL modulation bandwidth. The fundamental output of the VCO can be tuned from 27 GHz to 39 GHz, which corresponds to a frequency tuning range (FTR) of 36 %. We extract the 2nd harmonic in a non-invasive way using transformer. The measured phase noise (PN) at 1 MHz offset from the fundamental carrier varies across the tuning range from -100 dBc/Hz to -90 dBc/Hz. The VCO including output buffers dissipates 65 mW DC power from a single 1 V supply and consumes a chip area of 0.12 mm2.

A 42-mW, 45-nm SOI-CMOS single-chip radar sensor is flip-chip packaged with 4 RX and 2 TX antennas on a 7x7mm2 flexible interposer. It has 10$\%$ tuning range, -104 to -108 dBc/Hz phase noise at 10-MHz offset, 10-dB conversion gain per receiver and -7-dBm TX output power. The chip features a fundamental-frequency VCO and a static divide-by-8192 chain which is turned off 95% of the time to save DC power. Doppler and direction of arrival tests were conducted over distances of several cm.

This paper presents a highly selective integrated dielectric sensor with read-out circuit at 240 GHz in SiGe BiCMOS and back-side etching technology. The sensor is mainly configured with a resonator to perform bandpass frequency response which varied in accordance to the dielectric change of the sample under test. This variation can be sensed and recorded as the change of output voltage of an integrated 240 GHz IQ receiver. The demonstration of aforementioned function is verified by measuring the output of mixer when a sample is placed over the resonator.

A fast and simple permittivity measurement system at the terahertz wave band is proposed in this work. A 2-tone method is used to measure permittivity. To generate the 2-tone signal simply, a method using just a single frequency oscillator and LO leakage at the transmitter is proposed. To measure 2-tone phase difference at high speed, a self-heterodyne technique with a simple diode is applied in the receiver. The proposed system demonstrated a measurement time of 0.03 ms at 1 point, which is 1/200 compared to a conventional system, with an error of less than 6%.

An active mm-wave tag was manufactured in a SiGe BiCMOS process and operates in the 74-83GHz band with - 62dBm input sensitivity. It features a 28dB gain LNA with 9dB noise figure, a wake-up detector, a BPSK modulator and two variable gain output stages each driving a separate transmit antenna. The chip occupies 570μm × 880μm, consumes 25/10.8 mW in active/stand-by mode, and is flip-chip mounted on a 7mm×7mm flexible interposer with two transmit and one receive antenna.

This paper presents a millimeter-wave (125GHz) based ultra-short distance (~2mm) contactless wave-connector (CWC) for consumer interconnect applications. Conventional high-speed connectors in interconnect standard such as USB, HDMI, DP, and Thunderbolt are not only expensive, but also suffer poor performance in both mechanical reliability and signal integrity often becoming a bottleneck in high-performance computing systems. The proposed CWC exploits a 125GHz CMOS transmitter (TX), receiver (RX), and compact FR4 PCB antenna to realize high-speed (>10Gb/s), low-cost, and energy efficient connector solutions. An on-off keying (OOK) modulation is utilized for a non-coherent transceiver (TRX) architecture. In addition, antennas are designed on an FR4HR substrate for a compatibility with an existing infrastructure. The CMOS TX and RX is assembled with the antenna through a flipchip process. The demonstrated CWC draws a total of 60mW of power under 1.1V supply while transferring 14Gb/s of data rate, achieving 4.28pJ/bit energy efficiency.

To accommodate small-cell deployment in future 5G wireless communications, a magnitude-selective affine function based digital predistortion model for RF power amplifiers is proposed. This model has a very simple model structure and is easy to implement. Experimental results showed, by employing this model, substantial hardware resource reduction can be achieved without sacrificing performance in comparison with the existing models.

Compact multi-band RF transmitter solution will play a unique role in the forthcoming 4G-beyond and 5G wireless networks. The emerging RF class data convertor, i.e., RFDAC enables a promising single-chain multi-band RF transmitter solution. To combat the imperfections of practical nonlinear power amplifiers in the single-chain multi-band RF solution, we need multi-band RF signal conditioning unit. This paper presents a very compact single-chain multi-band digital predistortion (DPD) solution using only one under-sampling ADC and a low band-pass filter to replace the conventional DPD feedback paths. The experimental results verified the proposed compact multi-band DPD architecture. Preliminarily the proposed DPD scheme with a single ADC at 76.8MSPS sampling rate in the feedback path is able to provide satisfactory multi-band linearization performance below -55 dBc within 1GHz bandwidth.

In the paper, we propose a novel DPD model including thermal memory effects modeling. The model is based on CPWL functions that are multidimensional mapping from R^n to C^m, and predistorter coefficients are naturally nonlinear functions of the modeled thermal effects. Our tests show the CPWL-based DPD model with thermal memory effects modeling has roughly 5 dB gain for dynamic transmitted power of 4-carrier UMTS signal spanning 20 MHz.

In this paper, an advanced calibration routine is proposed to determine the frequency response of a feedback receiver over a targeted linearization bandwidth, when only sub-Nyquist (aliased) samples are available. A new approach is then devised to apply a direct learning algorithm along with the proposed receiver calibration routine, and thus linearize a millimeter wave power amplifier (PA), driven by a modulated signal, using digital pre-distortion (DPD) with a reduced feedback sampling rate. The proposed new calibration routine and DPD approach are successfully applied to linearize a PA under test, operating at 24GHz and driven by single carrier 16QAM and carrier aggregated LTE signals of 200MHz modulation bandwidth using a feedback receiver with sampling rates of 2Gsps, 1Gsps and 500Msps. Adjacent channel power ratio of about 49dBc and normalized mean square error of about 2% are obtained at the linearized PA output using the three sampling rates.

This paper proposes a technique for designing multitone signals that can recover the third order multiple input multiple output (MIMO) Volterra kernels. Multitone signals result in a spectrum that is a permutation of the sums of the input signal tones. This a priori knowledge is used in this paper to design multitone signals such that the output of the MIMO Volterra kernels does not overlap in the frequency domain, hence making it possible to recover these kernels from the output of the MIMO Volterra system. Recovering the MIMO Volterra kernels is not only valuable for stable and simpler identification but also in the development of low complexity linearization techniques.

In this paper, we demonstrate a compact Doherty power amplifier (DPA) in a 0.15-µm enhancement mode (E-mode) Gallium Arsenide (GaAs) pseudomorphic high electron mobility transistor (pHEMT) process at Ka-band. The 2-stage DPA uses an integrated broadside input coupler to miniaturize the die size to 2.86 mm2. The monolithic millimeter-wave integrated circuit (MMIC) DPA exhibits measured output power of 26 dBm and measured average gain of 12 dB. The gain bandwidth covers from 25.5 to 33 GHz. The measured peak power added efficiency (PAE) is 40% and the PAE at 6 dB output power back-off is 29%. Moreover, an adjacent channel power ratio (ACPR) of -45 dBc has been measured using a 20 MHz digitally modulated signal and digital predistortion (DPD).

In this paper, a high gain high efficiency 3-stacked power amplifier (PA) without the need for an output matching network is presented. With the transistors stacked in series, the drain-gate and drain-source voltage swings on each transistor is relaxed while a high output power is delivered. The stacked PA is designed such that the output can drive the load directly without any impedance matching network to save chip area, simplify the design, and avoid the loss introduced by the on-chip passive components. An adaptive bias network is integrated to dynamically adjust the bias of the PA according to the input power level that effectively enhances the efficiency at power backoff. Implemented in 90-nm CMOS process, the proposed PA features a power gain of 17.2 dB at 32 GHz, a saturated output power of 17.6 dBm, a peak power-added-efficiency (PAE) of 25.3%, and a PAE at P1dB of 11.5%.

This paper presents the design of an efficient two-stage millimeter-wave power amplifier (PA) using stacked field-effect transistors in 45nm silicon-on-insulator (SOI) CMOS technology. It highlights two major issues encountered when designing single-ended multistage PAs at millimeter frequencies (e.g., 60GHz), namely the significant source to ground parasitic inductance and the vulnerability to oscillation at low frequencies. The two-stage differential PA includes input, inter-stage and output matching networks implemented using RF transformers with a high coupling factor and reduced insertion losses. The PA demonstrator showed a 3-dB bandwidth equal to 12GHz (55–67GHz). The small signal gain, peak power added efficiency and peak output power were recorded as 14.5dB, 25% and 17.3dBm, respectively.

This paper reports on a distributed power amplifier (DPA) millimeter-wave integrated circuit (MMIC) with high output power, high gain, and low noise figure. The ultra-wide bandwidth MMIC is based on a 50-nm gate-length metamorphic high-electron-mobility transistor (mHEMT) technology. The DPA uses eight stacked-HEMT unit power cells and covers a frequency range of more than 0–110 GHz. Due to the stacking approach of the unit cells it is possible to reach high output power and high gain over the designed frequency range with a single DPA stage. The average small-signal gain is 19.7 dB over the entire frequency range from 0 to 119 GHz. The noise figure yields a value between 2.5–6.4 dB for frequencies from 0 to 98 GHz. The saturated output power achieves an average value of 17.5 dBm up to a frequency of 110 GHz, with a peak output power of 20 dBm.

This paper presents a double-stacked four-way combined W-band power amplifier (PA) in 0.13μm SiGe BiCMOS process with 3dB small-signal bandwidth between 86.6-103.3GHz. This chip achieves a saturated power (Psat) of 23 dBm at a peak PAE of 16.8% at 95 GHz with Psat of more than 21 dBm across 85-105 GHz. To the best of the authors’ knowledge, this is the highest efficiency reported for silicon-based PAs at these frequencies with output power greater than 23 dBm. This paper also demonstrates the modulation measurements of constellation schemes QPSK, 16-QAM and 64-QAM in the W-Band with data rates up to 12Gbps.

Building receivers (RXs) that operate above the transistor unity-power-gain frequency, f_max, is extremely challenging because an LNA-less architecture must be adopted. This paper reports on a 300-GHz CMOS RX operating above NMOS f_max. Its conversion gain, noise figure, and 3-dB bandwidth are, respectively, –19.5 dB, 27 dB, and 26.5 GHz. The RX achieved a wireless data rate of 36 Gb/s with 16QAM. It shows the potential of moderate-f_max CMOS technology to be used for ultrahigh-speed THz wireless communications.

This paper presents a phase shifter for beam steered systems at mmW frequencies. It is based on a IQ hybrid transformer feeding a vector modulator that weight the amplitude of the quadrature differential signals. A specific passive attenuator has been designed to improve the attenuation depth, the phase accuracy and the impedance matching. A CMOS 55nm circuit was measured, that cover the 360° phase shift with less than 1 dB gain imbalance and 5° phase imbalance. It covers the frequency band from 55 to 67 GHz and paves the way towards mobile millimeter wave high data rate telecommunication systems.

This paper presents a compact 213 GHz fundamental oscillator with an optimal embedding network that maximizes the output power. Fabricated in 65-nm bulk CMOS, the oscillator occupies a core area of only 7040 μm2, owing to the use of a compact low-loss capacitive transformer structure. The oscillator achieves 0.56-mW output power while consuming a DC current of 14.35mA from a 1-V power supply, representing a recording-breaking DC-to-RF efficiency of 3.9% amongst fundamental oscillators above 200 GHz.

A high output power and high fundamental frequency CMOS oscillator is presented in this paper. To increase output power, the source inductor at the core transistor is coupled with the drain inductor at the buffer transistor through a transformer. A capacitive load reduction circuit (CLRC) is also used to increase the fundamental oscillation frequency. The proposed single-core fundamental oscillator is implemented using 65 nm CMOS technology. The measurement results show a fundamental frequency of 194 GHz and maximum differential output power of 1.85 mW.

A G-Band single pole single throw (SPST) switch for low insertion loss and high isolation is proposed and fabricated using 65-nm CMOS technology. A grounded co-planar waveguide (GCPW) folded couple line topology is developed to improve the switch isolation and lower its insertion loss simultaneously. Based on this topology, this switch achieves minimum 2.4-dB insertion loss (IL) in G-Band with minimum 28.5-dB isolation (ISO). This switch consumes only 0.0067 mm2 chip area. To the authors’ knowledge, this CMOS SPST switch achieves the best performance among the published switches in bulk CMOS processes at this frequency.

This work presents compact, low power, broadband and high sensitivity CMOS power detectors targeted for multigigabit software defined radio applications. Two power detectors (referred to as high sensitivity detector and video detector) are implemented in standard 65 nm CMOS technology with resistive input matching. Both designs have a measured input matching bandwidth from very low frequencies up to 110 GHz. The peak measured detection sensitivity of high sensitivity detector is 67 dB whereas the video detector possesses more than 10 GHz video bandwidth (verified up to 6 GHz through measurements). The DC power consumption of the high sensitivity detector and the video detector is 0.029 mW and 0.8 mW, respectively. According to the best knowledge of the authors, the proposed designs demonstrate widest reported input matching bandwidth while possessing a compact footprint, wide video bandwidth and high detection sensitivity in a standard CMOS technology.

It is well-known that the isolation provided by a hybrid combiner defeats the active load-modulation mechanism between the carrier and peaking power amplifiers in a Doherty transmitter. In this paper, a hybrid combiner is used in combination with a lattice network to combine the carrier and peaking amplifier in order to manage load modulation between them. Both amplifiers have a driver stage. The driver amplifiers are tuned and biased so that the efficiency at 6-dB back-off power is peaked. The prototype exhibits an efficiency at peak power of 80.5% and an efficiency at 6-dB back-off of 70.5% with non-flat gain at 300-MHz designed frequency. Alternatively, the transmitter can be optimized for flat gain transfer characteristics scarifying efficiency enhancement at back-off power but still higher than a class-B amplifier.

This work presents a load modulated balanced amplifier (LMBA) that directly amplifies a modulated RF input. The architecture is based on the recently proposed LMBA technique, in which a control signal applied at the output hybrid of a balanced amplifier is used to modulate the apparent load impedance of the two main devices. Here, we eliminate the need for an externally-generated control signal. Instead, the control signal is directly and simply synthesized from a modulated RF input, allowing the architecture to function directly as an RFinput / RF-output power amplifier. The technique is demonstrated at 670-850 MHz with a peak CW output power of 42.5 dBm, and peak efficiency of 56.72%.

Increasing the efficiency of power amplifiers operating at various power levels in a multicarrier, wideband application is of utmost importance when the available supply power is limited. This is the typical case of solar-powered amplifiers intended for the extension of cellular coverage into buildings and for linear transponders. In this work, we propose a novel power control technique that is a variant of the well-known average power tracking. We use a sample of the output of the power amplifier to close the feedback loop that adjusts the supply voltage, allowing for a smaller variation of gain over supply voltage and the reuse of the power detector intended for automatic gain control.

Recent interest in radio frequencies below 500 kHz has created a need for new small-signal measurement hardware to convert low-level RF signals to drive baseband digital signal processing hardware and software. The IQ Near-Zero-IF architecture receiver described here translates a 7 kHz bandwidth RF input channel to baseband, with a 4 dB noise figure, 50 ohm input, 60 dB flat gain, and greater than 80 dB in-band dynamic range. Analog signal processing and cascaded selectivity result in an output signal band identical to the input band, except for frequency and gain. Analog IQ processing provides greater than 50 dB opposite sideband suppression. LO frequency stability supports coherent integration times of 4 seconds per bit.

This paper presents an extremely low cost, tube conformable, printed T-resonator based microwave level sensor, whose resonance frequency shifts by changing the level (vertical height) of fluids inside the tube. Printed T-resonator forms the frequency selective element of the tunable oscillator. Unlike typical band-pass resonators, T-resonator has a band-notch characteristics because of which it has been integrated with an unstable amplifying unit having negative resistance in the desired frequency range. Phase flattening technique has been introduced to maximize the frequency shift of the oscillator. With the help of this technique, we are able to enhance the percentage tuning of the oscillator manifolds which results into a level sensor with higher sensitivity. The interface level of fluids (oil and water in our case) causes a percentage change in oscillation frequency by more than 50% (112-168MHz) compared to maximum frequency shift of 8% reported earlier with dielectric tunable oscillators.

This paper presents an active transponder design at VHF band suitable for geological monitoring of boreholes drilled through ice sheets. In order to monitor the boreholes at great depth, this work proposes an active target based Frequency Modulated Continuous Wave (FMCW) radar location system. The proposed system maximises the target detection (e.g. radar cross section) and read range. To distinguish the transponder response from stationary clutter, the transponder modulates the received signal before re-transmission to the surface radar. The transponder achieves a bandwidth of 292 – 492 MHz with a gain between 2 – 4 dB. The transponder employs two novel antennas for the transmission and reception of the signal. The simulation results of the proposed antenna and the experimental results of the transponder are presented.

This paper presents a broadband and highly efficient class-G supply modulated amplifier system. The system covers the full LTE band 1805-1880 MHz. The core element is the class-G supply modulator which switches the supply voltage of the RF power amplifier between three discrete levels with a minimum pulse duration of 2.5 ns. Measurement results are presented for a carrier aggregated signal using five subcarriers with modulation bandwidths from 5 MHz to 20 MHz each. In combination with digital predistortion the system achieves 38.5% PAE with -41 dB EVM and -45 dB ACLR for a 75 MHz multicarrier signal with a PAPR of 10.4 dB at 38.5 dBm average output power. The total efficiency enhancement achieved by the class-G modulation is 13 percentage points.

This work presents a dynamic characterization of a multi-level Chireix outphasing (ML-CO) power amplifier (PA) with modulated signals. The ML-CO technique combines the advantages of envelope tracking and outphasing architectures by limiting the supply modulation to discrete levels (enabling use of an efficient power-DAC modulator) and using outphasing for fine amplitude control. We describe the development of an experimental test bench able to supply phase- and time-aligned modulated signals for outphasing and supply modulation simultaneously. Pulse characterization is used to design a multilevel memory-less polynomial DPD. The linearized ML-CO PA is demonstrated with 1.4 MHz and 10 MHz LTE signals at 9.7 GHz. For both signals, the average total power consumption is reduced by a factor of two when supply modulation is used. For the 9.3 dB PAR, 1.4 MHz signal the PA operates with 38% average drain efficiency at 0.54 W average output power.

This paper introduces bandwidth reduction methods for supply modulation when multiple broadband signals spread over a wide RF bandwidth are simultaneously amplified by a high-efficiency PA. With a CW signal at 9.8 GHz, the peak power is 8 W with a peak efficiency of 56% and a saturated gain greater than 23 dB. Three 16QAM signals with bandwidths of 1, 2 and 5 MHz, separated by 70 and 130 MHz and centered around 9.8 GHz have a combined envelope bandwidth of > 800 MHz and a PAR around 9.5 dB, which is too large for an efficient envelope modulator. We show that the tracking bandwidth can be significantly reduced when the envelopes of the individual signals are summed at baseband. Measured results show 42.4% PAE and 18.8% worstcase EVM when tracking is used, compared to 29.7% PAE and 14.4% EVM for a fixed supply.

We report a high efficiency multi-band Envelope-Tracking Power Amplifier (ET-PA) that supports modulation bandwidth up to 80MHz using real-time digital predistortion (RT-DPD). The ET-PA consists of a broadband RF-PA and a single-phase buck-converter. Both RF-PA and buck-converter were fabricated using a GaN HEMT process. The RT-DPD system can generate the input signals for both buck-converter and RF-PA, and capture the output signal for feedback. An FPGA is employed in the RT-DPD system to perform predistortion in a closed-loop fashion. The overall ET-PA achieves total efficiency of 32.1-35.5%, output power of 30-30.7dBm with 30V supply voltage over 0.9-2.15GHz. By using the RT-DPD, ACLR is improved to below -45dBc even under 80MHz modulated LTE signal with 6.5dB PAPR, maintaining high efficiency. To the authors’ best knowledge, this is the widest modulation bandwidth yet reported for an efficient and multi-band ET-PA.

We present the design, fabrication and measurement of the first attenuation-counter-propagating optical-phase-locked-loop (ACP-OPLL) photonic IC without balanced photodetectors for high dynamic range RF photonic links. The novel ACP-OPLL design significantly reduces fabrication complexity, cost and opti-cal loss. Preliminary measurement showed improved SFDR performance.

We present an ultrafast and high responsivity graphene photodetector that operates over a broad bandwidth from visible to infrared regime. Use of plasmonic nanoantennas as photodetector contact electrodes provides a strong concentration of photo-generated carriers near the contact electrodes. As a result, a large number of the photocarriers drift to the photodetector contact electrodes despite the short carrier lifetime of graphene, providing high responsivity levels. The photodetector is also designed to offer high speed operation by minimizing capacitive parasitics. We demonstrate broadband photodetection from 800 nm to 20 μm with operation speeds exceeding 50 GHz and responsivity levels as high as 0.6 A/W at 0.8 μm and 11.5 A/W at 20 μm. These results are the first demonstration of high-responsivity photodetection with such a broad operation bandwidth and high speed, enabled by plasmonic nanoantennas.

We present a 100-GHz integrated photoreceiver using an optical-to-radio converter and an enhancement-mode PHEMT amplifier driven by all optical resources without an external electric power supply. Technology for the simultaneous generation of radio and power was developed using a zero-bias operational uni-travelling carrier (UTC) high-speed photodetector. To improve the optical-to-electrical conversion efficiency, a 110-GHz enhancement-mode InP-PHEMT amplifier was also newly developed, which operates using an internal electric power supply in an optical-to-radio converter. Using a hybrid integration based on all optical resources, a +5.5 dBm RF output at 97 GHz was successfully achieved through the optical-to-radio conversion process. Herein, the two key devices and the integrated photoreceiver are discussed.

We present a novel photoconductive terahertz detector, which offers significantly higher detection bandwidths and sensitivities compared to the state-of-the art. The detector is based on 2D plasmonic nano-antenna arrays, which are designed to concentrate a major fraction of an incident terahertz and optical pump beam at the same nanoscale regions in their close proximity. When the optical pump beam excites the detector, a large number of photocarriers are drifted to the plasmonic nano-antennas by the induced terahertz field to form the output current of the detector. The nano-antennas are also designed to offer high terahertz electric field enhancement factors over a broad terahertz frequency range. As a result, high-sensitivity and broadband operation is achieved simultaneously. We experimentally demonstrate pulsed terahertz detection with record-high signal-to-noise ratios as high as 107 dB over a 5 THz frequency range, which is 50 times higher compared to the state-of-the art.